SiFive come with World first U500 and E500 Open Source RISC-V SoCs

[david]

SiFive will publish specifications for an SoC based high-performance Unix-capable cache-coherent 64-bit multiprocessor U500 and one using a microcontroller core E300 both based on work of the RISC-V Foundation. RISC-V instructions set is free, compared to $40,000 ARM license for startups using Cortex M0 MCU!

http://www.iot-tech.dev/full.php?ar=51

[david]

Tues1345 - Coreboot on RISC-V - Ron Minnich, Google


youtu.be/KnwZzbvp1c

Tues1515 - Building the RISC-V Software Ecosystem - Arun Thomas, BAE Systems


youtu.be/4HAL13Sztg8