Re: coreboot on ASRock H110M-DVS rev 3.0 and rev 2.0 and me_cleaner
Posted: Wed Sep 25, 2024 2:05 pm
Progress: E3-1270-V6 Xeon on Coreboot with Asrock H110 Pro BTC+
While using the me-region from the 1.10 bios cleaned with -S option, coreboot does give Serial Debug output, recognizes CPU but no POST the system but it stays ON, previous coreboot attempts it powered down instantly after powering on:
Succesfull bootlog for G3950 CPU, without libgfxinit nor asmedia-switch but with intelME Corporate 11.8.77.3664 (coffeetime cleaned and patched) vs 11.6.x.xxx consumer.
The "[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found" errors are also present on the functional rom but after that it loads
FSPS maybe FSPS.bin related? Try different FSP package or disable HyperThreading?
BTW: to make the E3-1270-V6 work on warm (re)boots on original Asrock OEM firmware, just follow the steps from "chinobino" at level1tech to use the "Disabled" Corporate Me version vs the Consumer Me version:
https://winraid.level1techs.com/t/use-t ... d/32510/88
While using the me-region from the 1.10 bios cleaned with -S option, coreboot does give Serial Debug output, recognizes CPU but no POST the system but it stays ON, previous coreboot attempts it powered down instantly after powering on:
Code: Select all
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG] CPU: Intel(R) Xeon(R) CPU E3-1270 v6 @ 3.80GHz
[DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f7
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 5918 (rev 05) is Kabylake DT 2
[DEBUG] PCH: device id a143 (rev 31) is H110
[DEBUG] IGD: device id ffff (rev ff) is Unknown
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x610000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 7
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: mcache @0xfef04f00 built for 21 files, used 0x444 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x355c0 size 0xdd10 in mcache @0xfef04f8c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 78 ms
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 romstage starting (log level: 7)...
[CRIT ] HECI: reset failed
[DEBUG] pm1_sts: 0101 pm1_en: 0000 pm1_cnt: 00001c00
[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
[DEBUG] TCO_STS: 0000 0000
[DEBUG] GEN_PMCON: e0040200 0000500a
[DEBUG] GBLRST_CAUSE: 00000000 00000000
[DEBUG] prev_sleep_state 5 (S5)
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: Found 'fspm.bin' @0x6ddc0 size 0x63000 in mcache @0xfef0519c
[DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
[INFO ] No memory dimm at address A4
[DEBUG] SPD @ 0x50
[INFO ] SPD: module type is DDR4
[INFO ] SPD: module part number is CT4G4DFS8213.C8FAR
[INFO ] SPD: banks 16, ranks 1, rows 15, columns 10, density 4096 Mb
[INFO ] SPD: device width 8 bits, bus width 64 bits
[INFO ] SPD: module size is 4096 MB (per channel)
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x7f7ff000 254 entries.
[DEBUG] IMD: root @ 0x7f7fec00 62 entries.
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x7fbff000 254 entries.
[DEBUG] IMD: root @ 0x7fbfec00 62 entries.
[DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000
[DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG] 1 DIMMs found
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x7f800000 0x800000
[DEBUG] Subregion 0: 0x7f800000 0x200000
[DEBUG] Subregion 1: 0x7fa00000 0x200000
[DEBUG] Subregion 2: 0x7fc00000 0x400000
[DEBUG] top_of_ram = 0x7f800000
[DEBUG] Normal boot
[INFO ] CBFS: Found 'fallback/postcar' @0xf5640 size 0x5d40 in mcache @0xfef05268
[DEBUG] Loading module at 0x7f3cf000 with entry 0x7f3cf031. filesize: 0x5988 memsize: 0xbcd8
[DEBUG] Processing 222 relocs. Offset value of 0x7d3cf000
[DEBUG] BS: romstage times (exec / console): total (unknown) / 210 ms
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: Found 'fallback/ramstage' @0x43340 size 0x1f35c in mcache @0x7f3dd0ec
[DEBUG] Loading module at 0x7f27e000 with entry 0x7f27e000. filesize: 0x406a0 memsize: 0x14f950
[DEBUG] Processing 4838 relocs. Offset value of 0x7b27e000
[DEBUG] BS: postcar times (exec / console): total (unknown) / 44 ms
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] microcode: sig=0x906e9 pf=0x2 revision=0xf7
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x35400 in mcache @0x7f3dd02c
[DEBUG] Skip microcode update
[INFO ] CBFS: Found 'fsps.bin' @0xd0e00 size 0x23ff2 in mcache @0x7f3dd2dc
[DEBUG] Detected 4 core, 8 thread CPU.
[DEBUG] Setting up SMI for CPU
[DEBUG] IED base = 0x7fc00000
[DEBUG] IED size = 0x00400000
[INFO ] Will perform SMM setup.
[INFO ] CPU: Intel(R) Xeon(R) CPU E3-1270 v6 @ 3.80GHz.
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] CPU: APIC: 00 enabled
[DEBUG] CPU: APIC: 01 enabled
[DEBUG] CPU: APIC: 02 enabled
[DEBUG] CPU: APIC: 03 enabled
[DEBUG] CPU: APIC: 04 enabled
[DEBUG] CPU: APIC: 05 enabled
[DEBUG] CPU: APIC: 06 enabled
[DEBUG] CPU: APIC: 07 enabled
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 7 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[INFO ] LAPIC 0x1 in XAPIC mode.
[DEBUG] done.
[INFO ] AP: slot 4 apic_id 1, MCU rev: 0x000000f7
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x5 in XAPIC mode.
[INFO ] LAPIC 0x4 in XAPIC mode.
[INFO ] AP: slot 3 apic_id 5, MCU rev: 0x000000f7
[INFO ] AP: slot 5 apic_id 4, MCU rev: 0x000000f7
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] LAPIC 0x3 in XAPIC mode.
[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x000000f7
[INFO ] AP: slot 2 apic_id 3, MCU rev: 0x000000f7
[INFO ] LAPIC 0x7 in XAPIC mode.
[INFO ] LAPIC 0x6 in XAPIC mode.
[INFO ] AP: slot 7 apic_id 7, MCU rev: 0x000000f7
[INFO ] AP: slot 6 apic_id 6, MCU rev: 0x000000f7
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
[DEBUG] smm_module_setup_stub: stack_top = 0x7f804000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f29e8f8
[DEBUG] Installing permanent SMM handler to 0x7f800000
[DEBUG] HANDLER [0x7f9ff000-0x7f9ffd9f]
[DEBUG] CPU 0
[DEBUG] ss0 [0x7f9fec00-0x7f9fefff]
[DEBUG] stub0 [0x7f9f7000-0x7f9f719f]
[DEBUG] CPU 1
[DEBUG] ss1 [0x7f9fe800-0x7f9febff]
[DEBUG] stub1 [0x7f9f6c00-0x7f9f6d9f]
[DEBUG] CPU 2
[DEBUG] ss2 [0x7f9fe400-0x7f9fe7ff]
[DEBUG] stub2 [0x7f9f6800-0x7f9f699f]
[DEBUG] CPU 3
[DEBUG] ss3 [0x7f9fe000-0x7f9fe3ff]
[DEBUG] stub3 [0x7f9f6400-0x7f9f659f]
[DEBUG] CPU 4
[DEBUG] ss4 [0x7f9fdc00-0x7f9fdfff]
[DEBUG] stub4 [0x7f9f6000-0x7f9f619f]
[DEBUG] CPU 5
[DEBUG] ss5 [0x7f9fd800-0x7f9fdbff]
[DEBUG] stub5 [0x7f9f5c00-0x7f9f5d9f]
[DEBUG] CPU 6
[DEBUG] ss6 [0x7f9fd400-0x7f9fd7ff]
[DEBUG] stub6 [0x7f9f5800-0x7f9f599f]
[DEBUG] CPU 7
[DEBUG] ss7 [0x7f9fd000-0x7f9fd3ff]
[DEBUG] stub7 [0x7f9f5400-0x7f9f559f]
[DEBUG] stacks [0x7f800000-0x7f803fff]
[DEBUG] Loading module at 0x7f9ff000 with entry 0x7f9ff026. filesize: 0xd90 memsize: 0xda0
[DEBUG] Processing 81 relocs. Offset value of 0x7f9ff000
[DEBUG] Loading module at 0x7f9f7000 with entry 0x7f9f7000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG] Processing 9 relocs. Offset value of 0x7f9f7000
[DEBUG] smm_module_setup_stub: stack_top = 0x7f804000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG] SMM Module: placing smm entry code at 7f9f6c00, cpu # 0x1
[DEBUG] SMM Module: placing smm entry code at 7f9f6800, cpu # 0x2
[DEBUG] SMM Module: placing smm entry code at 7f9f6400, cpu # 0x3
[DEBUG] SMM Module: placing smm entry code at 7f9f6000, cpu # 0x4
[DEBUG] SMM Module: placing smm entry code at 7f9f5c00, cpu # 0x5
[DEBUG] SMM Module: placing smm entry code at 7f9f5800, cpu # 0x6
[DEBUG] SMM Module: placing smm entry code at 7f9f5400, cpu # 0x7
[DEBUG] SMM Module: stub loaded at 7f9f7000. Will call 0x7f9ff026
[DEBUG] Clearing SMI status registers
[DEBUG] SMI_STS: PM1
[DEBUG] PM1_STS: PWRBTN TMROF
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ef000, cpu = 0
[DEBUG] In relocation handler: CPU 0
[DEBUG] New SMBASE=0x7f9ef000 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee000, cpu = 4
[DEBUG] In relocation handler: CPU 4
[DEBUG] New SMBASE=0x7f9ee000 IEDBASE=0x7fc00000
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ed800, cpu = 6
[DEBUG] In relocation handler: CPU 6
[DEBUG] New SMBASE=0x7f9ed800 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ed400, cpu = 7
[DEBUG] In relocation handler: CPU 7
[DEBUG] New SMBASE=0x7f9ed400 IEDBASE=0x7fc00000
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9edc00, cpu = 5
[DEBUG] In relocation handler: CPU 5
[DEBUG] New SMBASE=0x7f9edc00 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee400, cpu = 3
[DEBUG] In relocation handler: CPU 3
[DEBUG] New SMBASE=0x7f9ee400 IEDBASE=0x7fc00000
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9eec00, cpu = 1
[DEBUG] In relocation handler: CPU 1
[DEBUG] New SMBASE=0x7f9eec00 IEDBASE=0x7fc00000
[DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7f9ee800, cpu = 2
[DEBUG] In relocation handler: CPU 2
[DEBUG] New SMBASE=0x7f9ee800 IEDBASE=0x7fc00000
[DEBUG] Relocation complete.
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[INFO ] Turbo is available but hidden
[INFO ] Turbo is available and visible
[DEBUG] Skip microcode update
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #4
[INFO ] Initializing CPU #1
[INFO ] Initializing CPU #2
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #1 initialized
[DEBUG] Skip microcode update
[INFO ] CPU #2 initialized
[INFO ] Initializing CPU #3
[INFO ] Initializing CPU #5
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #3 initialized
[DEBUG] Skip microcode update
[INFO ] CPU #5 initialized
[INFO ] Initializing CPU #7
[INFO ] Initializing CPU #6
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #7 initialized
[DEBUG] Skip microcode update
[INFO ] CPU #6 initialized
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #4 initialized
[INFO ] bsp_do_flight_plan done after 723 msecs.
[DEBUG] CPU: frequency set to 4200 MHz
[DEBUG] Enabling SMIs.
[DEBUG] Locking SMM.
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 473 / 466 ms
[DEBUG] IA32_FEATURE_CONTROL status: locked
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
Code: Select all
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG] CPU: Intel(R) Celeron(R) CPU G3950 @ 3.00GHz
[DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f7
[DEBUG] CPU: AES supported, TXT NOT supported, VT supported
[DEBUG] MCH: device id 590f (rev 06) is Kabylake-S
[DEBUG] PCH: device id a143 (rev 31) is H110
[DEBUG] IGD: device id 5902 (rev 04) is Kaby Lake DT GT1F
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x610000.
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 7
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: mcache @0xfef04f00 built for 20 files, used 0x414 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x355c0 size 0xdd10 in mcache @0xfef04f8c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 78 ms
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 romstage starting (log level: 7)...
[CRIT ] HECI: reset failed
[DEBUG] pm1_sts: 0001 pm1_en: 0000 pm1_cnt: 00001c00
[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
[DEBUG] TCO_STS: 0000 0000
[DEBUG] GEN_PMCON: e0040200 0000500e
[DEBUG] GBLRST_CAUSE: 00000000 00000000
[DEBUG] prev_sleep_state 5 (S5)
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: Found 'fspm.bin' @0x62dc0 size 0x63000 in mcache @0xfef0516c
[DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
[INFO ] No memory dimm at address A4
[DEBUG] SPD @ 0x50
[INFO ] SPD: module type is DDR4
[INFO ] SPD: module part number is CT4G4DFS8213.C8FAR
[INFO ] SPD: banks 16, ranks 1, rows 15, columns 10, density 4096 Mb
[INFO ] SPD: device width 8 bits, bus width 64 bits
[INFO ] SPD: module size is 4096 MB (per channel)
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x7afff000 254 entries.
[DEBUG] IMD: root @ 0x7affec00 62 entries.
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x7b3ff000 254 entries.
[DEBUG] IMD: root @ 0x7b3fec00 62 entries.
[DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
[DEBUG] 1 DIMMs found
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x7b000000 0x800000
[DEBUG] Subregion 0: 0x7b000000 0x200000
[DEBUG] Subregion 1: 0x7b200000 0x200000
[DEBUG] Subregion 2: 0x7b400000 0x400000
[DEBUG] top_of_ram = 0x7b000000
[DEBUG] Normal boot
[INFO ] CBFS: Found 'fallback/postcar' @0xea640 size 0x5d40 in mcache @0xfef05238
[DEBUG] Loading module at 0x7abcf000 with entry 0x7abcf031. filesize: 0x5988 memsize: 0xbcd8
[DEBUG] Processing 222 relocs. Offset value of 0x78bcf000
[DEBUG] BS: romstage times (exec / console): total (unknown) / 215 ms
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: Found 'fallback/ramstage' @0x43340 size 0x1b5c7 in mcache @0x7abdd0ec
[DEBUG] Loading module at 0x7aa86000 with entry 0x7aa86000. filesize: 0x38560 memsize: 0x147790
[DEBUG] Processing 4538 relocs. Offset value of 0x76a86000
[DEBUG] BS: postcar times (exec / console): total (unknown) / 44 ms
[NOTE ] coreboot-24.08-285-gb95c4986356e-dirty Wed Sep 25 03:03:04 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG] Normal boot
[DEBUG] microcode: sig=0x906e9 pf=0x2 revision=0xf7
[DEBUG] FMAP: area COREBOOT found @ 610200 (2031104 bytes)
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x35400 in mcache @0x7abdd02c
[DEBUG] Skip microcode update
[INFO ] CBFS: Found 'fsps.bin' @0xc5e00 size 0x23ff2 in mcache @0x7abdd2ac
[DEBUG] Detected 2 core, 2 thread CPU.
[DEBUG] Setting up SMI for CPU
[DEBUG] IED base = 0x7b400000
[DEBUG] IED size = 0x00400000
[INFO ] Will perform SMM setup.
[INFO ] CPU: Intel(R) Celeron(R) CPU G3950 @ 3.00GHz.
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] CPU: APIC: 00 enabled
[DEBUG] CPU: APIC: 01 enabled
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 1 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x2 in XAPIC mode.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x000000f7
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
[DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7aaa0cef
[DEBUG] Installing permanent SMM handler to 0x7b000000
[DEBUG] HANDLER [0x7b1ff000-0x7b1ffd9f]
[DEBUG] CPU 0
[DEBUG] ss0 [0x7b1fec00-0x7b1fefff]
[DEBUG] stub0 [0x7b1f7000-0x7b1f719f]
[DEBUG] CPU 1
[DEBUG] ss1 [0x7b1fe800-0x7b1febff]
[DEBUG] stub1 [0x7b1f6c00-0x7b1f6d9f]
[DEBUG] stacks [0x7b000000-0x7b000fff]
[DEBUG] Loading module at 0x7b1ff000 with entry 0x7b1ff026. filesize: 0xd90 memsize: 0xda0
[DEBUG] Processing 81 relocs. Offset value of 0x7b1ff000
[DEBUG] Loading module at 0x7b1f7000 with entry 0x7b1f7000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG] Processing 9 relocs. Offset value of 0x7b1f7000
[DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG] SMM Module: placing smm entry code at 7b1f6c00, cpu # 0x1
[DEBUG] SMM Module: stub loaded at 7b1f7000. Will call 0x7b1ff026
[DEBUG] Clearing SMI status registers
[DEBUG] SMI_STS: PM1
[DEBUG] PM1_STS: TMROF
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ef000, cpu = 0
[DEBUG] In relocation handler: CPU 0
[DEBUG] New SMBASE=0x7b1ef000 IEDBASE=0x7b400000
[DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1eec00, cpu = 1
[DEBUG] In relocation handler: CPU 1
[DEBUG] New SMBASE=0x7b1eec00 IEDBASE=0x7b400000
[DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[INFO ] Turbo is unavailable
[DEBUG] Skip microcode update
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[DEBUG] CPU: vendor Intel device 906e9
[DEBUG] CPU: family 06, model 9e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] Skip microcode update
[INFO ] CPU #1 initialized
[INFO ] bsp_do_flight_plan done after 262 msecs.
[DEBUG] Enabling SMIs.
[DEBUG] Locking SMM.
[DEBUG] VMX status: enabled
[DEBUG] VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] IA32_FEATURE_CONTROL status: locked
[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 93 / 323 ms
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found
[INFO ] FSPS, status=0x00000000
[INFO ] ITSS IRQ Polarities Before:
[INFO ] IPC0: 0x00ff4000
[INFO ] IPC1: 0x00000007
[INFO ] IPC2: 0x00000000
[INFO ] IPC3: 0x00000000
[INFO ] ITSS IRQ Polarities After:
[INFO ] IPC0: 0x00ff4000
[INFO ] IPC1: 0x00000007
[INFO ] IPC2: 0x00000000
[INFO ] IPC3: 0x00000000
[INFO ] Found PCIe Root Port #5 at PCI: 00:1c.0.
[INFO ] Found PCIe Root Port #7 at PCI: 00:1c.6.
[NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:00:1c.0) which was enabled in devicetree, removing and disabling.
[INFO ] Remapping PCIe Root Port #5 from PCI: 00:00:1c.4 to new function number 0.
[NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #6 (originally PCI: 00:00:1c.5) which was enabled in devicetree, removing and disabling.
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 26 / 152 ms
[INFO ] Enumerating buses...
[DEBUG] Root Device scanning...
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 00000000 enabled
[DEBUG] DOMAIN: 00000000 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG] PCI: 00:00:00.0 [8086/590f] enabled
[DEBUG] PCI: 00:00:01.0 subordinate bus PCI Express
[DEBUG] PCI: 00:00:01.0 [8086/1901] enabled
[DEBUG] PCI: 00:00:02.0 [8086/5902] enabled
[DEBUG] PCI: 00:00:04.0 [8086/1903] enabled
[DEBUG] PCI: 00:00:14.0 [8086/a12f] enabled
[DEBUG] PCI: 00:00:14.2 [8086/a131] enabled
[INFO ] PCI: Static device PCI: 00:00:16.0 not found, disabling it.
[DEBUG] PCI: 00:00:17.0 [8086/a102] enabled
[DEBUG] PCI: 00:00:1c.0 [8086/a114] enabled
[DEBUG] PCI: 00:00:1c.6 [8086/a116] enabled
[DEBUG] PCI: 00:00:1f.0 [8086/a143] enabled
[DEBUG] PCI: 00:00:1f.1 [8086/a120] enabled
[DEBUG] PCI: 00:00:1f.2 [8086/a121] enabled
[DEBUG] PCI: 00:00:1f.3 [8086/a170] enabled
[DEBUG] PCI: 00:00:1f.4 [8086/a123] enabled
[DEBUG] PCI: 00:00:1f.5 [8086/a124] enabled
[DEBUG] PCI: 00:00:1f.6 [8086/15b8] enabled
[DEBUG] GPIO: 0 enabled
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:00:01.1
[WARN ] PCI: 00:00:01.2
[WARN ] PCI: 00:00:05.0
[WARN ] PCI: 00:00:07.0
[WARN ] PCI: 00:00:08.0
[WARN ] PCI: 00:00:13.0
[WARN ] PCI: 00:00:14.1
[WARN ] PCI: 00:00:14.3
[WARN ] PCI: 00:00:15.0
[WARN ] PCI: 00:00:15.1
[WARN ] PCI: 00:00:15.2
[WARN ] PCI: 00:00:15.3
[WARN ] PCI: 00:00:16.0
[WARN ] PCI: 00:00:16.1
[WARN ] PCI: 00:00:16.2
[WARN ] PCI: 00:00:16.3
[WARN ] PCI: 00:00:16.4
[WARN ] PCI: 00:00:19.0
[WARN ] PCI: 00:00:19.1
[WARN ] PCI: 00:00:19.2
[WARN ] PCI: 00:00:1e.0
[WARN ] PCI: 00:00:1e.1
[WARN ] PCI: 00:00:1e.2
[WARN ] PCI: 00:00:1e.3
[WARN ] PCI: 00:00:1e.4
[WARN ] PCI: 00:00:1e.5
[WARN ] PCI: 00:00:1e.6
[WARN ] PCI: 00:00:1f.7
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] PCI: 00:00:01.0 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG] PCI: 00:01:00.0 [1002/665f] enabled
[DEBUG] PCI: 00:01:00.1 [1002/aac0] enabled
[INFO ] Enabling Common Clock Configuration
[INFO ] PCIE CLK PM is not supported by endpoint
[INFO ] ASPM: Enabled L0s and L1
[DEBUG] PCI: 00:01:00.0: No LTR support
[INFO ] Enabling Common Clock Configuration
[INFO ] PCIE CLK PM is not supported by endpoint
[INFO ] ASPM: Enabled L0s and L1
[DEBUG] PCI: 00:01:00.1: No LTR support
[INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 62 msecs
[DEBUG] PCI: 00:00:02.0 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs
[DEBUG] PCI: 00:00:14.0 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs
[DEBUG] PCI: 00:00:1c.0 scanning...
[INFO ] PCI: 00:00:1c.0: Enabled LTR
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 19 msecs
[DEBUG] PCI: 00:00:1c.6 scanning...
[INFO ] PCI: 00:00:1c.6: Enabled LTR
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
[INFO ] PCI: 00:00:1c.6: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1c.6 finished in 19 msecs
[DEBUG] PCI: 00:00:1f.0 scanning...
[DEBUG] PNP: 002e.0 enabled
[DEBUG] PNP: 004e.0 enabled
[DEBUG] PNP: 002e.0 scanning...
[DEBUG] PNP: 002e.1 enabled
[DEBUG] PNP: 002e.2 enabled
[DEBUG] PNP: 002e.3 enabled
[DEBUG] PNP: 002e.5 enabled
[DEBUG] PNP: 002e.6 disabled
[DEBUG] PNP: 002e.7 enabled
[DEBUG] PNP: 002e.107 enabled
[DEBUG] PNP: 002e.207 enabled
[DEBUG] PNP: 002e.8 disabled
[DEBUG] PNP: 002e.108 enabled
[DEBUG] PNP: 002e.308 disabled
[DEBUG] PNP: 002e.408 disabled
[DEBUG] PNP: 002e.708 enabled
[DEBUG] PNP: 002e.9 enabled
[DEBUG] PNP: 002e.109 enabled
[DEBUG] PNP: 002e.209 enabled
[DEBUG] PNP: 002e.309 enabled
[DEBUG] PNP: 002e.a enabled
[DEBUG] PNP: 002e.b enabled
[DEBUG] PNP: 002e.d disabled
[DEBUG] PNP: 002e.e disabled
[DEBUG] PNP: 002e.f disabled
[DEBUG] PNP: 002e.14 disabled
[DEBUG] PNP: 002e.16 disabled
[DEBUG] PNP: 002e.116 disabled
[DEBUG] PNP: 002e.316 enabled
[DEBUG] PNP: 002e.416 disabled
[DEBUG] PNP: 002e.516 enabled
[DEBUG] PNP: 002e.616 enabled
[DEBUG] PNP: 002e.716 disabled
[DEBUG] scan_bus: bus PNP: 002e.0 finished in 107 msecs
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 124 msecs
[DEBUG] PCI: 00:00:1f.2 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs
[DEBUG] PCI: 00:00:1f.3 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
[DEBUG] PCI: 00:00:1f.4 scanning...
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 0 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 520 msecs
[DEBUG] scan_bus: bus Root Device finished in 539 msecs
[INFO ] done
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 552 ms
[INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG] FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
[INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 18 ms
[DEBUG] found VGA at PCI: 00:01:00.0
[DEBUG] Setting up VGA for PCI: 00:01:00.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:00:01.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ] Allocating resources...
[INFO ] Reading resources...
[DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000
[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000
[DEBUG] SA MMIO resource: DMIBAR -> base = 0xfed18000, size = 0x00001000
[DEBUG] SA MMIO resource: EPBAR -> base = 0xfed19000, size = 0x00001000
[DEBUG] SA MMIO resource: GDXCBAR -> base = 0xfed84000, size = 0x00001000
[DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
[DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000
[DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000
[INFO ] Available memory above 4GB: 2048M
[INFO ] Done reading resources.
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
[DEBUG] PCI: 00:00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:01:00.0 20 * [0x0 - 0xff] io
[DEBUG] PCI: 00:00:01.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:00:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:01:00.0 24 * [0x0 - 0x3ffff] mem
[DEBUG] PCI: 00:01:00.0 30 * [0x40000 - 0x5ffff] mem
[DEBUG] PCI: 00:01:00.1 10 * [0x60000 - 0x63fff] mem
[DEBUG] PCI: 00:00:01.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:00:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0xfffffff] prefmem
[DEBUG] PCI: 00:01:00.0 18 * [0x10000000 - 0x107fffff] prefmem
[DEBUG] PCI: 00:00:01.0 prefmem: size: 10800000 align: 28 gran: 20 limit: ffffffff done
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000280 limit 000002ff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 00000080 limit 0000008f io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.0 00 base 0000002e limit 0000002f io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.3 60 base 000002f8 limit 000002ff io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
[DEBUG] avoid_fixed_resources: PNP: 002e.b 62 base 00000000 limit 00000001 io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 40 base 00001800 limit 000018ff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
[INFO ] DOMAIN: 00000000: Resource ranges:
[INFO ] * Base: 1000, Size: 800, Tag: 100
[INFO ] * Base: 1900, Size: d6a0, Tag: 100
[INFO ] * Base: efc0, Size: 1040, Tag: 100
[DEBUG] PCI: 00:00:01.0 1c * [0xf000 - 0xffff] limit: ffff io
[DEBUG] PCI: 00:00:02.0 20 * [0xefc0 - 0xefff] limit: efff io
[DEBUG] PCI: 00:00:17.0 20 * [0xef80 - 0xef9f] limit: ef9f io
[DEBUG] PCI: 00:00:17.0 18 * [0xef78 - 0xef7f] limit: ef7f io
[DEBUG] PCI: 00:00:17.0 1c * [0xef74 - 0xef77] limit: ef77 io
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base e0000000 limit efffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed10000 limit fed17fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base fed18000 limit fed18fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed19000 limit fed19fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed84000 limit fed84fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed91000 limit fed91fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 7b000000 limit 7fffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 100000000 limit 17fffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 48 base fe000000 limit fe00ffff mem (fixed)
[INFO ] DOMAIN: 00000000: Resource ranges:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200
[INFO ] * Base: 180000000, Size: 7e80000000, Tag: 200
[DEBUG] PCI: 00:00:01.0 24 * [0xc0000000 - 0xd07fffff] limit: d07fffff prefmem
[DEBUG] PCI: 00:00:02.0 18 * [0xb0000000 - 0xbfffffff] limit: bfffffff prefmem
[DEBUG] PCI: 00:00:02.0 10 * [0xdf000000 - 0xdfffffff] limit: dfffffff mem
[DEBUG] PCI: 00:00:01.0 20 * [0xdef00000 - 0xdeffffff] limit: deffffff mem
[DEBUG] PCI: 00:00:1f.6 10 * [0xdeee0000 - 0xdeefffff] limit: deefffff mem
[DEBUG] PCI: 00:00:14.0 10 * [0xdeed0000 - 0xdeedffff] limit: deedffff mem
[DEBUG] PCI: 00:00:1f.3 20 * [0xdeec0000 - 0xdeecffff] limit: deecffff mem
[DEBUG] PCI: 00:00:04.0 10 * [0xdeeb8000 - 0xdeebffff] limit: deebffff mem
[DEBUG] PCI: 00:00:1f.2 10 * [0xdeeb4000 - 0xdeeb7fff] limit: deeb7fff mem
[DEBUG] PCI: 00:00:1f.3 10 * [0xdeeb0000 - 0xdeeb3fff] limit: deeb3fff mem
[DEBUG] PCI: 00:00:17.0 10 * [0xdeeae000 - 0xdeeaffff] limit: deeaffff mem
[DEBUG] PCI: 00:00:14.2 10 * [0xdeead000 - 0xdeeadfff] limit: deeadfff mem
[DEBUG] PCI: 00:00:1f.5 10 * [0xdeeac000 - 0xdeeacfff] limit: deeacfff mem
[DEBUG] PCI: 00:00:17.0 24 * [0xdeeab000 - 0xdeeab7ff] limit: deeab7ff mem
[DEBUG] PCI: 00:00:17.0 14 * [0xdeeaa000 - 0xdeeaa0ff] limit: deeaa0ff mem
[DEBUG] PCI: 00:00:1f.4 10 * [0xdeea9000 - 0xdeea90ff] limit: deea90ff mem
[DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff done
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[DEBUG] PCI: 00:01:00.0 20 * [0xf000 - 0xf0ff] limit: f0ff io
[DEBUG] PCI: 00:01:00.0 10 * [0xc0000000 - 0xcfffffff] limit: cfffffff prefmem
[DEBUG] PCI: 00:01:00.0 18 * [0xd0000000 - 0xd07fffff] limit: d07fffff prefmem
[DEBUG] PCI: 00:01:00.0 24 * [0xdef00000 - 0xdef3ffff] limit: def3ffff mem
[DEBUG] PCI: 00:01:00.0 30 * [0xdef40000 - 0xdef5ffff] limit: def5ffff mem
[DEBUG] PCI: 00:01:00.1 10 * [0xdef60000 - 0xdef63fff] limit: def63fff mem
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
[DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 buio
[DEBUG] PCI: 00:00:01.0 24 <- [0x00000000c0000000 - 0x00000000d07fffff] size 0x10800000 gran 0x14 seg 00 buprefmem
[DEBUG] PCI: 00:00:01.0 20 <- [0x00000000def00000 - 0x00000000deffffff] size 0x00100000 gran 0x14 seg 00 bumem
[DEBUG] PCI: 00:01:00.0 10 <- [0x00000000c0000000 - 0x00000000cfffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 00:01:00.0 18 <- [0x00000000d0000000 - 0x00000000d07fffff] size 0x00800000 gran 0x17 prefmem64
[DEBUG] PCI: 00:01:00.0 20 <- [0x000000000000f000 - 0x000000000000f0ff] size 0x00000100 gran 0x08 io
[DEBUG] PCI: 00:01:00.0 24 <- [0x00000000def00000 - 0x00000000def3ffff] size 0x00040000 gran 0x12 mem
[DEBUG] PCI: 00:01:00.0 30 <- [0x00000000def40000 - 0x00000000def5ffff] size 0x00020000 gran 0x11 romem
[DEBUG] PCI: 00:01:00.1 10 <- [0x00000000def60000 - 0x00000000def63fff] size 0x00004000 gran 0x0e mem64
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000df000000 - 0x00000000dfffffff] size 0x01000000 gran 0x18 mem64
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000b0000000 - 0x00000000bfffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000efc0 - 0x000000000000efff] size 0x00000040 gran 0x06 io
[DEBUG] PCI: 00:00:04.0 10 <- [0x00000000deeb8000 - 0x00000000deebffff] size 0x00008000 gran 0x0f mem64
[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000deed0000 - 0x00000000deedffff] size 0x00010000 gran 0x10 mem64
[DEBUG] PCI: 00:00:14.2 10 <- [0x00000000deead000 - 0x00000000deeadfff] size 0x00001000 gran 0x0c mem64
[DEBUG] PCI: 00:00:17.0 10 <- [0x00000000deeae000 - 0x00000000deeaffff] size 0x00002000 gran 0x0d mem
[DEBUG] PCI: 00:00:17.0 14 <- [0x00000000deeaa000 - 0x00000000deeaa0ff] size 0x00000100 gran 0x08 mem
[DEBUG] PCI: 00:00:17.0 18 <- [0x000000000000ef78 - 0x000000000000ef7f] size 0x00000008 gran 0x03 io
[DEBUG] PCI: 00:00:17.0 1c <- [0x000000000000ef74 - 0x000000000000ef77] size 0x00000004 gran 0x02 io
[DEBUG] PCI: 00:00:17.0 20 <- [0x000000000000ef80 - 0x000000000000ef9f] size 0x00000020 gran 0x05 io
[DEBUG] PCI: 00:00:17.0 24 <- [0x00000000deeab000 - 0x00000000deeab7ff] size 0x00000800 gran 0x0b mem
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bumem
[DEBUG] PCI: 00:00:1c.6 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio
[DEBUG] PCI: 00:00:1c.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem
[DEBUG] PCI: 00:00:1c.6 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bumem
[DEBUG] PNP: 002e.1 13 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
[DEBUG] PNP: 002e.1 14 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
[INFO ] done.
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 1 / 12 ms
[WARN ] HECI: CSE device 16.0 is disabled
[DEBUG] ME: Version: Unavailable
[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 0 / 9 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[INFO ] CPU TDP = 51 Watts
[INFO ] CPU PL1 = 51 Watts
[INFO ] CPU PL2 = 91 Watts
[DEBUG] PCI: 00:00:00.0 init finished in 11 msecs
[DEBUG] PCI: 00:00:02.0 init
[INFO ] CBFS: Found 'vbt.bin' @0xe9e40 size 0x49c in mcache @0x7abdd2e0
[INFO ] Found a VBT of 4284 bytes
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[DEBUG] PCI: 00:00:02.0 init finished in 19 msecs
[DEBUG] PCI: 00:00:04.0 init
[DEBUG] PCI: 00:00:04.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:14.0 init
[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:14.2 init
[DEBUG] PCI: 00:00:14.2 init finished in 0 msecs
[DEBUG] PCI: 00:00:1c.0 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs
[DEBUG] PCI: 00:00:1c.6 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1c.6 init finished in 4 msecs
[DEBUG] PCI: 00:00:1f.0 init
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
[DEBUG] IOAPIC: ID = 0x00
[DEBUG] IOAPIC: 120 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
[DEBUG] PCI: 00:00:1f.0 init finished in 23 msecs
[DEBUG] PCI: 00:00:1f.2 init
[DEBUG] RTC Init
[INFO ] Set power on after power failure.
[DEBUG] apm_control: Disabling ACPI.
[DEBUG] APMC done.
[DEBUG] Disabling Deep S3
[DEBUG] Disabling Deep S3
[DEBUG] Disabling Deep S4
[DEBUG] Disabling Deep S4
[DEBUG] Disabling Deep S5
[DEBUG] Disabling Deep S5
[DEBUG] PCI: 00:00:1f.2 init finished in 33 msecs
[DEBUG] PCI: 00:00:1f.3 init
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
[DEBUG] PCI: 00:00:1f.4 init
[DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs
[DEBUG] PCI: 00:00:1f.5 init
[DEBUG] PCI: 00:00:1f.5 init finished in 0 msecs
[DEBUG] PCI: 00:00:1f.6 init
[DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs
[DEBUG] PCI: 00:01:00.0 init
[WARN ] CBFS: 'pci1002,665f.rom' not found.
[DEBUG] Option ROM address for PCI: 00:01:00.0 = def40000
[DEBUG] Copying VGA ROM Image from 0xdef40000 to 0xc0000, 0x10000 bytes
[DEBUG] Calling Option ROM...
[DEBUG] ... Option ROM returned.
[DEBUG] VBE: Getting information about VESA mode 4118
[DEBUG] VBE: Unsupported video mode 118!
[DEBUG] Supported Video Mode list for OpRom:
[DEBUG] 110
[DEBUG] 111
[DEBUG] 113
[DEBUG] 114
[DEBUG] 116
[DEBUG] 117
[DEBUG] 119
[DEBUG] 11a
[DEBUG] 165
[DEBUG] 166
[DEBUG] 121
[DEBUG] 122
[DEBUG] 123
[DEBUG] 124
[DEBUG] 145
[DEBUG] 146
[DEBUG] 175
[DEBUG] 176
[DEBUG] 1d2
[DEBUG] 1d4
[DEBUG] 1d8
[DEBUG] 1d9
[WARN ] VBE Warning: Error from VGA BIOS in vbe_get_mode_info
[WARN ] VBE Warning: Could not get VBE graphics mode info.
[DEBUG] VGA Option ROM was run
[DEBUG] PCI: 00:01:00.0 init finished in 1911 msecs
[DEBUG] PCI: 00:01:00.1 init
[DEBUG] PCI: 00:01:00.1 init finished in 0 msecs
[DEBUG] PNP: 002e.1 init
[DEBUG] PNP: 002e.1 init finished in 0 msecs
[DEBUG] PNP: 002e.2 init
[DEBUG] PNP: 002e.2 init finished in 0 msecs
[DEBUG] PNP: 002e.3 init
[DEBUG] PNP: 002e.3 init finished in 0 msecs
[DEBUG] PNP: 002e.5 init
[DEBUG] Keyboard init...
[DEBUG] PS/2 keyboard initialized on primary channel
[DEBUG] PNP: 002e.5 init finished in 416 msecs
[DEBUG] PNP: 002e.7 init
[DEBUG] PNP: 002e.7 init finished in 0 msecs
[DEBUG] PNP: 002e.107 init
[DEBUG] PNP: 002e.107 init finished in 0 msecs
[DEBUG] PNP: 002e.207 init
[DEBUG] PNP: 002e.207 init finished in 0 msecs
[DEBUG] PNP: 002e.108 init
[DEBUG] PNP: 002e.108 init finished in 0 msecs
[DEBUG] PNP: 002e.708 init
[DEBUG] PNP: 002e.708 init finished in 0 msecs
[DEBUG] PNP: 002e.9 init
[DEBUG] PNP: 002e.9 init finished in 0 msecs
[DEBUG] PNP: 002e.109 init
[DEBUG] PNP: 002e.109 init finished in 0 msecs
[DEBUG] PNP: 002e.209 init
[DEBUG] PNP: 002e.209 init finished in 0 msecs
[DEBUG] PNP: 002e.309 init
[DEBUG] PNP: 002e.309 init finished in 0 msecs
[DEBUG] PNP: 002e.a init
[DEBUG] PNP: 002e.a init finished in 0 msecs
[DEBUG] PNP: 002e.b init
[DEBUG] PNP: 002e.b init finished in 0 msecs
[DEBUG] PNP: 002e.316 init
[DEBUG] PNP: 002e.316 init finished in 0 msecs
[DEBUG] PNP: 002e.516 init
[DEBUG] PNP: 002e.516 init finished in 0 msecs
[DEBUG] PNP: 002e.616 init
[DEBUG] PNP: 002e.616 init finished in 0 msecs
[INFO ] Devices initialized
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 2220 / 497 ms
[INFO ] Finalize devices...
[DEBUG] PCI: 00:00:02.0 final
[DEBUG] PCI: 00:00:17.0 final
[DEBUG] PCI: 00:00:1f.2 final
[DEBUG] PCI: 00:00:1f.4 final
[INFO ] Devices finalized
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 21 ms
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x5fd40 size 0x2db7 in mcache @0x7abdd1b8
[WARN ] CBFS: 'fallback/slic' not found.
[INFO ] ACPI: Writing ACPI tables at 7aa17000.
[DEBUG] ACPI: * FACS
[DEBUG] SCI is IRQ 9, GSI 9
[DEBUG] ACPI: * FACP
[DEBUG] ACPI: added table 1/32, length now 44
[DEBUG] Found 1 CPU(s) with 2/2 physical/logical core(s) each.
[DEBUG] PSS: 3000MHz power 51000 control 0x1e00 status 0x1e00
[DEBUG] PSS: 2800MHz power 46488 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 38025 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 30195 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 23024 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 16422 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10377 control 0x800 status 0x800
[DEBUG] PSS: 3000MHz power 51000 control 0x1e00 status 0x1e00
[DEBUG] PSS: 2800MHz power 46488 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 38025 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 30195 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 23024 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 16422 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 10377 control 0x800 status 0x800
[DEBUG] PCI space above 4GB MMIO is at 0x180000000, len = 0x7e80000000
[DEBUG] Empty min sleep state array returned
[INFO ] Returning default LPI constraint package
[INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in
[DEBUG] \_SB.PCI0.LPCB.SIO0: PNP: 002e.0
[DEBUG] \_SB.PCI0.LPCB.SIO0.L010: PNP: 002e.1
[DEBUG] \_SB.PCI0.LPCB.SIO0.L020: PNP: 002e.2
[DEBUG] \_SB.PCI0.LPCB.SIO0.L030: PNP: 002e.3
[DEBUG] \_SB.PCI0.LPCB.SIO0.L050: PNP: 002e.5
[DEBUG] \_SB.PCI0.LPCB.SIO0.L070: PNP: 002e.7
[DEBUG] PNP: 002e.107: Ignoring virtual LDN
[DEBUG] PNP: 002e.207: Ignoring virtual LDN
[DEBUG] PNP: 002e.108: Ignoring virtual LDN
[DEBUG] PNP: 002e.708: Ignoring virtual LDN
[DEBUG] \_SB.PCI0.LPCB.SIO0.L090: PNP: 002e.9
[DEBUG] PNP: 002e.109: Ignoring virtual LDN
[DEBUG] PNP: 002e.209: Ignoring virtual LDN
[DEBUG] PNP: 002e.309: Ignoring virtual LDN
[DEBUG] \_SB.PCI0.LPCB.SIO0.L0A0: PNP: 002e.a
[DEBUG] \_SB.PCI0.LPCB.SIO0.L0B0: PNP: 002e.b
[DEBUG] PNP: 002e.316: Ignoring virtual LDN
[DEBUG] PNP: 002e.516: Ignoring virtual LDN
[DEBUG] PNP: 002e.616: Ignoring virtual LDN
[WARN ] CBFS: 'pci1002,665f.rom' not found.
[DEBUG] Option ROM address for PCI: 00:01:00.0 = def40000
[DEBUG] ACPI: * SSDT
[DEBUG] ACPI: added table 2/32, length now 52
[DEBUG] ACPI: * MCFG
[DEBUG] ACPI: added table 3/32, length now 60
[DEBUG] ACPI: * LPIT
[DEBUG] ACPI: added table 4/32, length now 68
[DEBUG] IOAPIC: 120 interrupts
[DEBUG] SCI is IRQ 9, GSI 9
[DEBUG] ACPI: * APIC
[DEBUG] ACPI: added table 5/32, length now 76
[DEBUG] ACPI: * SPCR
[DEBUG] ACPI: added table 6/32, length now 84
[DEBUG] current = 7aa1b4e0
[DEBUG] ACPI: * DMAR
[DEBUG] ACPI: added table 7/32, length now 92
[DEBUG] acpi_write_dbg2_pci_uart: Device not found
[DEBUG] ACPI: * HPET
[DEBUG] ACPI: added table 8/32, length now 100
[DEBUG] Copying initialized VBIOS image from 0x000c0000
[DEBUG] ACPI: * VFCT at 7aa1b5b0
[DEBUG] ACPI: added table 9/32, length now 108
[INFO ] ACPI: done.
[DEBUG] ACPI tables: 83488 bytes.
[DEBUG] smbios_write_tables: 7a9ff000
[DEBUG] SMBIOS firmware version is set to coreboot_version: '24.08-285-gb95c4986356e-dirty'
[INFO ] Create SMBIOS type 16
[INFO ] Create SMBIOS type 17
[INFO ] Create SMBIOS type 20
[DEBUG] SMBIOS tables: 847 bytes.
[DEBUG] Writing table forward entry at 0x00000500
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d53a
[DEBUG] Writing coreboot table at 0x7aa3b000
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG] 3. 0000000000100000-000000007a9fefff: RAM
[DEBUG] 4. 000000007a9ff000-000000007aa85fff: CONFIGURATION TABLES
[DEBUG] 5. 000000007aa86000-000000007abcdfff: RAMSTAGE
[DEBUG] 6. 000000007abce000-000000007affffff: CONFIGURATION TABLES
[DEBUG] 7. 000000007b000000-000000007fffffff: RESERVED
[DEBUG] 8. 00000000e0000000-00000000efffffff: RESERVED
[DEBUG] 9. 00000000fd000000-00000000fe00ffff: RESERVED
[DEBUG] 10. 00000000fed10000-00000000fed19fff: RESERVED
[DEBUG] 11. 00000000fed80000-00000000fed84fff: RESERVED
[DEBUG] 12. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG] 13. 0000000100000000-000000017fffffff: RAM
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x800000
[DEBUG] Wrote coreboot table at: 0x7aa3b000, 0x48c bytes, checksum ba5f
[DEBUG] coreboot table: 1188 bytes.
[DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
[DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
[DEBUG] FSP MEMORY 2. 0x7abfe000 0x00400000
[DEBUG] CONSOLE 3. 0x7abde000 0x00020000
[DEBUG] RO MCACHE 4. 0x7abdd000 0x00000414
[DEBUG] TIME STAMP 5. 0x7abdc000 0x00000910
[DEBUG] MEM INFO 6. 0x7abdb000 0x00000f48
[DEBUG] AFTER CAR 7. 0x7abce000 0x0000d000
[DEBUG] RAMSTAGE 8. 0x7aa85000 0x00149000
[DEBUG] REFCODE 9. 0x7aa57000 0x0002e000
[DEBUG] SMM BACKUP 10. 0x7aa47000 0x00010000
[DEBUG] IGD OPREGION11. 0x7aa43000 0x000030bc
[DEBUG] COREBOOT 12. 0x7aa3b000 0x00008000
[DEBUG] ACPI 13. 0x7aa17000 0x00024000
[DEBUG] VGA ROM #0 14. 0x7aa07000 0x00010000
[DEBUG] SMBIOS 15. 0x7a9ff000 0x00008000
[DEBUG] IMD small region:
[DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
[DEBUG] FSP RUNTIME 1. 0x7affebe0 0x00000004
[DEBUG] FMAP 2. 0x7affea80 0x0000015e
[DEBUG] POWER STATE 3. 0x7affea40 0x00000040
[DEBUG] FSPM VERSION 4. 0x7affea20 0x00000004
[DEBUG] ROMSTAGE 5. 0x7affea00 0x00000004
[DEBUG] ROMSTG STCK 6. 0x7affe940 0x000000a8
[DEBUG] ACPI GNVS 7. 0x7affe900 0x00000038
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 178 / 631 ms
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] MTRR: Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
[DEBUG] 0x000000007b000000 - 0x00000000bfffffff size 0x45000000 type 0
[DEBUG] 0x00000000c0000000 - 0x00000000d07fffff size 0x10800000 type 1
[DEBUG] 0x00000000d0800000 - 0x00000000ffffffff size 0x2f800000 type 0
[DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
[DEBUG] MTRR: default type WB/UC MTRR counts: 11/6.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
[DEBUG] MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
[DEBUG] MTRR: 4 base 0x00000000d0000000 mask 0x0000007fff800000 type 1
[DEBUG] MTRR: 5 base 0x0000000100000000 mask 0x0000007f80000000 type 6
[ERROR] Null dereference at eip: 0x7aaa109e
[INFO ] LAPIC 0x2 in XAPIC mode.
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
[DEBUG] MTRR: TEMPORARY Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
[DEBUG] 0x000000007b000000 - 0x00000000ff7fffff size 0x84800000 type 0
[DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5
[DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
[DEBUG] MTRR: default type WB/UC MTRR counts: 11/5.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
[DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
[DEBUG] MTRR: 3 base 0x00000000ff800000 mask 0x0000007fff800000 type 5
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR check
[DEBUG] Fixed MTRRs : Enabled
[DEBUG] Variable MTRRs: Enabled
[DEBUG] BS: BS_WRITE_TABLES exit times (exec / console): 58 / 306 ms
[INFO ] CBFS: Found 'fallback/payload' @0xf0400 size 0x11c5f in mcache @0x7abdd37c
[DEBUG] Checking segment from ROM address 0xfff0062c
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
[DEBUG] Checking segment from ROM address 0xfff00648
[DEBUG] Loading segment from ROM address 0xfff0062c
[DEBUG] code (compression=1)
[DEBUG] New segment dstaddr 0x000de1a0 memsize 0x21e60 srcaddr 0xfff00664 filesize 0x11c27
[DEBUG] Loading Segment: addr: 0x000de1a0 memsz: 0x0000000000021e60 filesz: 0x0000000000011c27
[DEBUG] using LZMA
[DEBUG] Loading segment from ROM address 0xfff00648
[DEBUG] Entry Point 0x000fd246
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 9 / 69 ms
[DEBUG] Finalizing chipset.
[WARN ] HECI: CSE device 16.0 is disabled
[INFO ] Disabling Heci using PCR
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 19 ms
[DEBUG] mp_park_aps done after 0 msecs.
[WARN ] VBE Warning: Could not set VBE text mode.
[DEBUG] Jumping to boot code at 0x000fd246(0x7aa3b000)
SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
BUILD: gcc: (coreboot toolchain v2024-08-28_0abdb8b8a9) 14.2.0 binutils: (GNU Binutils) 2.43.1
SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
BUILD: gcc: (coreboot toolchain v2024-08-28_0abdb8b8a9) 14.2.0 binutils: (GNU Binutils) 2.43.1
Found coreboot cbmem console @ 7abde000
Found mainboard ASROCK H110M
Relocating init from 0x000df900 to 0x799f1c20 (size 54080)
Found CBFS header at 0xffe1022c
multiboot: eax=7aabde78, ebx=7aabde44
Found 17 PCI devices (max PCI bus is 03)
Copying SMBIOS from 0x7a9ff000 to 0x000f5b40
Copying SMBIOS 3.0 from 0x7a9ff020 to 0x000f5b20
Copying ACPI RSDP from 0x7aa17000 to 0x000f5af0
table(50434146)=0x7aa1a050 (via xsdt)
Using pmtimer, ioport 0x1808
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
PCI: XHCI at 00:14.0 (mmio 0xdeed0000)
XHCI init: regs @ 0xdeed0000, 20 ports, 64 slots, 32 byte contexts
XHCI protocol USB 2.00, 10 ports (offset 1), def 3011
XHCI protocol USB 3.00, 4 ports (offset 17), def 3000
XHCI extcap 0xc0 @ 0xdeed8070
XHCI extcap 0x1 @ 0xdeed846c
XHCI extcap 0xc6 @ 0xdeed84f4
XHCI extcap 0xc7 @ 0xdeed8500
XHCI extcap 0xc2 @ 0xdeed8600
XHCI extcap 0xa @ 0xdeed8700
XHCI extcap 0xc3 @ 0xdeed8740
XHCI extcap 0xc4 @ 0xdeed8800
XHCI extcap 0xc5 @ 0xdeed8900
AHCI controller at 00:17.0, iobase 0xdeeab000, irq 11
Searching bootorder for: /pci@i0cf8/*@17/drive@0/disk@0
AHCI/0: Set transfer mode to UDMA-6
Searching bootorder for: HALT
Found 0 lpt ports
Found 2 serial ports
Searching bios-geometry for: /pci@i0cf8/*@17/drive@0/disk@0
AHCI/0: registering: "AHCI/0: KINGSTON RBUSNS8180DS364GG ATA-10 Hard-Disk (61057 MiBytes)"
XHCI port #2: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
xhci_realloc_pipe: reconf ctl endpoint pkt size: 8 -> 64
USB mouse initialized
PS2 keyboard initialized
All threads complete.
Scan for option roms
Press ESC for boot menu.
Searching bootorder for: HALT
drive 0x000f5a80: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=125045424
Space available for UMB: d0000-eb800, f5360-f5a80
Returned 16629760 bytes of ZoneHigh
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007a9db000 = 1 RAM
4: 000000007a9db000 - 0000000080000000 = 2 RESERVED
5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
6: 00000000fd000000 - 00000000fe010000 = 2 RESERVED
7: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
8: 00000000fed80000 - 00000000fed85000 = 2 RESERVED
9: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
10: 0000000100000000 - 0000000180000000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
FSPS maybe FSPS.bin related? Try different FSP package or disable HyperThreading?
BTW: to make the E3-1270-V6 work on warm (re)boots on original Asrock OEM firmware, just follow the steps from "chinobino" at level1tech to use the "Disabled" Corporate Me version vs the Consumer Me version:
https://winraid.level1techs.com/t/use-t ... d/32510/88
